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ISL59532
Data Sheet February 24, 2006 FN7432.0
32 x 32 Video Crosspoint
The ISL59532 is a 32 x 32 integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) insertion. The ISL59532 is ideal for routing video signals in security and video-on-demand systems. This device operates from a single +5V supply. Any output can be switched to any of the 32 input video signal sources. OSD information can be inserted into any output through an internal, dedicated fast 2:1 mux (15ns switching times) located before the output buffer. Also, any input can be broadcast to all 32 outputs. Each output can be tri-stated and its gain set to +1 or +2. The ISL59532 offers a -3dB signal bandwidth of 320MHz. The differential gain and differential phase of 0.025%, along with 0.1dB flatness out to 50MHz, make the ISL59532 suitable for many video applications. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPITM-compatible three-wire serial interface. The ISL59532 interface is set up to facilitate both fast updates and initialization. On power-up, all outputs are initialized in the disabled state to avoid output conflicts within the user system. For capacitor-coupled applications, the inputs include a clamp circuit that restores the input level to an externally applied reference. The ISL59532 is available in a 356 Ld BGA package and specified over an extended -40C to +85C temperature range. The ISL59532 has single-supply signal operation. It can accommodate voltages from 0V to 3.5V at the inputs and 0V to 4V at the outputs. It also has an input clamp with external group reference that can be used for AC-coupled applications. A fully differential input version of this device is also available, ISL59533.
Features
* 32 x 32 non-blocking switch with buffered inputs and outputs * Operates from a single +5V supply * Output gain switchable x1 or x2 * SPI digital interface * Tri-state output * -90dB Isolation at 6MHz * 0.025%/0.05 dG/dP * Pb-free plus anneal available (RoHS compliant)
Applications
* Security camera switching * RGB routing * HDTV routing
Ordering Information
PART NUMBER ISL59532IKEZ (See Note) TAPE & REEL PACKAGE 356 Ld BGA (Pb-free) PKG. DWG. # V356.27x27A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59532 Pinout
ISL59532 (356 LD BGA) TOP VIEW
A B C D E F G H J K L M N P R T U V W Y
In24 NC In23 In22 In21 In20 In19 In18 In17 In16 In15 In14 In13 In12 In11 In10 In9 In8 NC In7
In25 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC In6
In26 NC
In27 NC
In28 NC
In29 NC
In30 NC
In31 NC
Overt31 Over30 Over29 Overt28 Out27 Out26 Out25 Out24 Out31 Out30 Out29 Out28 Over27 Over26 Over25 Over24 Vover31 Vover30 Vover29 Vover28 Vover27 Vover26 Vover25 Vover24 Vover23 Out23 Overt23
Vlogic
Vs Vs Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs Vs
Vover22 Out22 Overt22 Vover21 Out21 Over21 Vover20 Out20 Over20 Vover19 Over19 Out19 Vover18 Over18 Out18 Vover17 Over17 Out17 Vover16 Over16 Out16 Vover15 Out15 Over15 Vover14 Out14 Over14 Vover13 Out13 Over13 Vover12 Out12 Over12 Vover11 Over11 Out11 Vover10 Over10 Out10 Vover9 Over9 Out9 Out8
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Vm Gnd
Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs
Sout Reset Senb Clock Sdi Ref
Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Spare1 Spare0 NC In5 NC In4 NC In3 NC In2 NC In1 NC In0
Diode Vover0 Vover1 Vover2 Vover3 Vover4 Vover5 Vover6 Vover7 Vover8 Over8 Over0 Over1 Over2 Over3 Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7
Over4 Over5 Over6 Over7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
= NO BALLS PAD NAME "GND" IS THE SAME AS PACKAGE OR BALL NAME "GROUND" OR "G" PAD NAME "VS" IS THE SAME AS PACKAGE OR BALL NAME "POWER" OR "P" PAD X, Y IS FROM PAD CENTER ALL PADS ARE 70 x 70
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FN7432.0 February 24, 2006
ISL59532
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . . 5.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VS VD AV Supply Range Digital Supply Gain
VS = 5V CONDITION MIN 4.5 Establishes serial output high level AV = 1, RL = 500 AV = 2, RL = 150 1.2 0.97 1.94 -1.5 1 2 1 0.5 0 0 -10 -10 -25 -70 60 25 -5 -7 0 0 100 35 80 Enabled, no load current Disabled 600 1.6 700 2.2 TYP MAX 5.5 5.5 1.03 2.06 1.5 1.0 3.5 4.0 0 -5 25 70 UNIT V V V/V V/V % % V V A A mV mV mA mA dB mA mA
DESCRIPTION
GM
Gain Matching (to average of all other outputs) Input Voltage Range Output Voltage Range Input Bias Current
AV = 1 AV = 2 AV = 1 AV = 2, RL = 150 Clamp off Clamp enabled, VIN = VREF + 0.5V
VIN VOUT IB
VOS
Output Offset Voltage
AV = 1 AV = 2
IOUT
Output Current
Sourcing, RL = 10 to GND Sinking, RL to 2.5V
PSRR IS
Power Supply Rejection Ratio Supply Current
AC Electrical Specifications
PARAMETER BW -3dB BW 0.1dB SR TS Glitch Tover dG dP Xt VN DESCRIPTION 3dB Bandwidth 0.1dB Bandwidth Slew Rate Settling Time to 0.1% Switching Glitch, Peak Overlay Delay Time Diff Gain Diff Phase Hostile Crosstalk Input Noise Voltage CONDITION VOUT = 200mVP-P, AV = 2 VOUT = 200mVP-P, AV = 2 VOUT = 2VP-P, AV = 2 VOUT = 2VP-P, AV = 2 AV = 1 Beginning of output transition AV = 2, RL = 150 AV = 2, RL = 150 6MHz 360 MIN TYP 320 50 520 12 40 6 0.025 0.05 -85 18 MAX UNIT MHz MHz V/s ns mV ns %
dB nV/Hz
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FN7432.0 February 24, 2006
ISL59532 Pin Descriptions
NAME IN4 IN5 IN6 IN7 REF GND SDI VS IN8 IN9 IN10 IN11 VS GND IN12 IN13 IN14 IN15 SCLK VS ENA GND IN16 IN17 IN18 IN19 VS GND IN20 IN21 IN22 IN23 RESET VS SDO GND IN24 IN25 IN26 NUMBER Y4 Y3 Y2 Y1 M3 GND L3 VS V1 U1 T1 R1 VS GND P1 N1 M1 L1 K3 VS J3 GND K1 J1 H1 G1 VS GND F1 E1 D1 C1 H3 VS G3 GND A1 A2 A3 Input Input Input Input Clamp reference input Ground Serial data input Power supply Input Input Input Input Power supply Ground Input Input Input Input Serial data clock Power supply Serial enable-inverted Ground Input Input Input Input Power supply Ground Input Input Input Input Reset input Power supply Serial data output Ground Input Input Input DESCRIPTION
Pin Descriptions (Continued)
NAME IN27 INPUTTEST GND GND VS VS VLOGIC IN28 IN29 IN30 IN31 VSL VGL VS GND OVER31 VOVER31 OUT31 OVER30 VOVER30 OUT30 OVER29 VOVER29 OUT29 OVER28 VOVER28 OUT28 GND VS OUT27 VOVER27 OVER27 OUT26 VOVER26 OVER26 OUT25 VOVER25 OVER25 OUT24 NUMBER A4 NONE GND GND VS VS D3 A5 A6 A7 A8 VS GND VS GND A10 C10 B10 A11 C11 B11 A12 C12 B12 A13 C13 B13 GND VS A14 C14 B14 A15 C15 B15 A16 C16 B16 A17 Input Manufacturing test pin - leave open Ground Ground Power supply Power supply Logic power supply for serial output driver Input Input Input Input Power supply Ground Power supply Ground Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Ground Power supply Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Output DESCRIPTION
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FN7432.0 February 24, 2006
ISL59532 Pin Descriptions (Continued)
NAME VOVER24 OVER24 GND OUTTEST3 VS OVER23 VOVER23 OUT23 OVER22 VOVER22 OUT22 OVER21 VOVER21 OUT21 OVER20 VOVER20 OUT20 GND VS OUT19 VOVER19 OVER19 OUT18 VOVER18 OVER18 OUT17 VOVER17 OVER17 OUT16 VOVER16 OVER16 OUTTEST2 GND VS OVER15 VOVER15 OUT15 OVER14 VOVER14 OUT14 NUMBER C17 B17 GND NONE VS C20 C18 C19 D20 D18 D19 E20 E18 E19 F20 F18 F19 GND VS G20 G18 G19 H20 H18 H19 J20 J18 J19 K20 K18 K19 NONE GND VS L20 L18 L19 M20 M18 M19 DESCRIPTION Overlay analog input Overlay logic control Ground Manufacturing test pin-leave open Power supply Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Ground Power supply Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Manufacturing test pin-leave open Ground Power supply Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output
Pin Descriptions (Continued)
NAME OVER13 VOVER13 OUT13 OVER12 VOVER12 OUT12 GND VS OUT11 VOVER11 OVER11 OUT10 VOVER10 OVER10 OUT9 VOVER9 OVER9 OUT8 VOVER8 OVER8 VS OUTTEST1 GND OVER7 VOVER7 OUT7 OVER6 VOVER6 OUT6 OVER5 VOVER5 OUT5 OVER4 VOVER4 OUT4 VS GND OUT3 VOVER3 OVER3 NUMBER N20 N18 N19 P20 P18 P19 GND VS R20 R18 R19 T20 T18 T19 U20 U18 U19 V20 V18 V19 VS NONE GND Y17 V17 W17 Y16 V16 W16 Y15 V15 W15 Y14 V14 W14 VS GND Y13 V13 W13 DESCRIPTION Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Ground Power supply Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Power supply Manufacturing test pin-leave open Ground Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Overlay logic control Overlay analog input Output Power supply Ground Output Overlay analog input Overlay logic control
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FN7432.0 February 24, 2006
ISL59532 Pin Descriptions (Continued)
NAME OUT2 VOVER2 OVER2 OUT1 VOVER1 OVER1 OUT0 VOVER0 OVER0 VS OUTTEST0 GND IN0 IN1 IN2 IN3 DIODE VS GND VS GND SPARE0 SPARE1 INPUTTEST BUS NUMBER Y12 V12 W12 Y11 V11 W11 Y10 V10 W10 VS NONE GND Y8 Y7 Y6 Y5 V9 VS GND VS GND V6 V5 NONE Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Output Overlay analog input Overlay logic control Power supply Manufacturing test pin-leave open Ground Input Input Input Input Anode of a ground-connected diode: useful for measuring die temperature Power supply Ground Power supply Ground Not assigned-do not connect Not assigned-do not connect Manufacturing test pin-leave open DESCRIPTION
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FN7432.0 February 24, 2006
ISL59532 Typical Performance Curves
33pF 27pF 22pF 15pF 10pF
MUX mode AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0
MUX mode AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0
33pF 27pF 22pF 15pF
4.7pF 0pF
10pF 4.7pF 0pF
FIGURE 1. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, MUX MODE
FIGURE 2. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, MUX MODE
100 150
100 150
500 500 1.07k MUX mode AV = 1 CL = 0 INPUT_CH 0 OUTPUT_CH 0 MUX mode AV = 2 CL = 0 INPUT_CH 0 OUTPUT_CH 0 1.07k
FIGURE 3. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, MUX MODE
FIGURE 4. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, MUX MODE
Overlay mode AV = 1 RL = 100 CL=0pF INPUT_CH 31 OUTPUT_CH 31
Overlay mode AV = 2 RL = 100 CL=0pF INPUT_CH 31 OUTPUT_CH 31
FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 1
FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 2
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FN7432.0 February 24, 2006
ISL59532 Typical Performance Curves (Continued)
Broadcast mode AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0
33pF 27pF 22pF 15pF
Broadcast mode AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0
33pF 27pF 22pF 15pF
10pF 4.7pF 0pF
10pF 4.7pF 0pF
FIGURE 7. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, BROADCAST MODE
FIGURE 8. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, BROADCAST MODE
100 150
100
503 1.07k Broadcast mode AV = 1 CL = 0 INPUT_CH 0 OUTPUT_CH 0 Broadcast mode AV = 2 CL = 0 INPUT_CH 0 OUTPUT_CH 0 1.07k
FIGURE 9A. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, BROADCAST MODE
FIGURE 10. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, BROADCAST MODE
AV = 1 RL = 100 CL = 0
ADJACENT INPUT_CH30 OUTPUT_CH31
AV = 2 RL = 100 CL = 0
ADJACENT INPUT_CH30 OUTPUT_CH31
ALL HOSTILE INPUT_CH0 OUTPUT_CH31
ALL HOSTILE INPUT_CH0 OUTPUT_CH31
FIGURE 11. CROSSTALK - AV = 1
FIGURE 12. CROSSTALK - AV = 2
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FN7432.0 February 24, 2006
ISL59532 Typical Performance Curves (Continued)
AV=2 RL=100 INPUT_CH 0 OUTPUT_CH 0 VOP-P =2V
THD 2nd HD
AV=2 RL=100 INPUT_CH 0 OUTPUT_CH 0 FREQUENCY = 1MHz
THD 2nd HD
3rd HD 3rd HD
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs VOUT_P-P
FIGURE 15. DISABLE OUTPUT IMPEDANCE
FIGURE 16. ENABLE OUTPUT IMPEDANCE
MUX MODE AV = 1 RL = 100 INPUT_CH 31 OUTPUT_CH 31 FALL TIME 2.65ns
RISE TIME 2.35ns
MUX MODE AV = 1 RL = 100 INPUT_CH 31 OUTPUT_CH 31
FIGURE 17. RISE TIME - AV = 1
FIGURE 18. FALL TIME - AV = 1
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FN7432.0 February 24, 2006
ISL59532 Typical Performance Curves (Continued)
MUX MODE AV = 2 RL = 100 INPUT_CH 31 OUTPUT_CH 31
FALL TIME 2.35ns
RISE TIME 2.19ns
MUX MODE AV = 2 RL = 100 INPUT_CH 31 OUTPUT_CH 31
FIGURE 19. RISE TIME - AV = 2
FIGURE 20. FALL TIME - AV = 2
MUX MODE AV = 1 RL=100 INPUT_CH 31 OUTPUT_CH 31 SLEW RATE 448V/s SLEW RATE -436V/s
MUX MODE AV = 1 RL=100 INPUT_CH 31 OUTPUT_CH 31
FIGURE 21. RISING SLEW RATE - AV = 1
FIGURE 22. FALLING SLEW RATE - AV = 1
MUX MODE AV = 2 RL=100 INPUT_CH 31 OUTPUT_CH 31 SLEW RATE 531V/s
SLEW RATE -511V/s
MUX MODE AV = 2 RL=100 INPUT_CH 31 OUTPUT_CH 31
FIGURE 23. RISING SLEW RATE - AV = 2
FIGURE 24. FALLING SLEW RATE - AV = 2
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FN7432.0 February 24, 2006
ISL59532 Typical Performance Curves (Continued)
OUTPUT
OUTPUT
OVERLAY LOGIC INPUT
OVERLAY LOGIC INPUT
FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME
FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME
AV = 2 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
FIGURE 27. DIFFERENTIAL GAIN, AV = 2
FIGURE 28. DIFFERENTIAL PHASE, AV = 2
AV = 2 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
FIGURE 29. DIFFERENTIAL GAIN, AV = 2
FIGURE 30. DIFFERENTIAL PHASE, AV = 2
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FN7432.0 February 24, 2006
ISL59532 Typical Performance Curves (Continued)
AV = 1 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
FIGURE 31. DIFFERENTIAL GAIN, AV = 1
FIGURE 32. DIFFERENTIAL PHASE, AV = 1
AV = 1 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
FIGURE 33. DIFFERENTIAL GAIN, AV = 1
FIGURE 34. DIFFERENTIAL GAIN, AV = 1
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
FIGURE 35. DIFFERENTIAL GAIN, AV = 2
FIGURE 36. DIFFERENTIAL PHASE, AV = 2
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FN7432.0 February 24, 2006
ISL59532 Typical Performance Curves (Continued)
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
FIGURE 37. DIFFERENTIAL GAIN, AV = 2
FIGURE 38. DIFFERENTIAL PHASE, AV = 2
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
FIGURE 39. DIFFERENTIAL GAIN, AV = 1
FIGURE 40. DIFFERENTIAL PHASE, AV = 1
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
FIGURE 41. DIFFERENTIAL GAIN, AV = 1
FIGURE 42. DIFFERENTIAL PHASE, AV = 1
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FN7432.0 February 24, 2006
ISL59532 Typical Performance Curves (Continued)
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, AV = 2
FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, AV = 2
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, AV = 1
FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, AV = 1
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FN7432.0 February 24, 2006
3dB Bandwidth, MUX Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 262 224 217 211 277 267 268 288 271 269 277 273 274 274 255 264 268 298 292 289 290 304 299 307 304 198 309 299 300 292 290 286 283 278 268 265 255 281 266 285 268 196 264 269 267 199 206 214 238 230 238 220 280 287 271 247 282 265 290 286 276 277 264 288 275 350 336 216 277 285 283 281 252 252 274 272 283 274 292 299 296 298 308 326 311 221 309 313 311 293 297 294 283 271 258 256 272 272 275 267 271 278 247 290 268 272 259 203 214 1 2 3 4 5 270 6 7 8 9 10 268 11 12 13 14 15 235 16 17 18 19 20 236 21 22 23 24 25 235 214 26 27 28 29 30 31 236
OUTPUT CHANNELS
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FN7432.0 February 24, 2006
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ISL59532
3dB Bandwidth, MUX Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 304 291 290 302 353 346 349 371 372 360 363 351 350 337 348 340 327 360 353 348 349 366 360 366 363 280 366 357 360 348 348 343 337 325 330 339 344 351 347 371 361 289 354 350 338 288 290 295 311 313 314 297 336 345 360 300 350 321 348 338 345 355 350 354 353 381 377 334 360 366 357 348 318 308 314 353 348 341 352 358 353 356 364 372 366 173 364 367 368 348 354 352 352 351 350 317 336 350 363 340 366 376 310 370 348 348 331 295 294 1 2 3 4 5 323 6 7 8 9 10 324 11 12 13 14 15 305 16 17 18 19 20 313 21 22 23 24 25 320 290 26 27 28 29 30 31 308
OUTPUT CHANNELS
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FN7432.0 February 24, 2006
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ISL59532
3dB Bandwidth, Broadcast Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 196 185 172 161 165 160 152 141 133 133 132 130 125 125 127 125 124 119 116 113 114 112 108 107 106 107 108 107 104 104 105 107 106 110 108 103 98 98 98 99 101 99 97 95 87 86 84 102 98 97 96 96 96 96 94 99 97 89 88 85 129 124 118 109 109 110 112 113 110 107 106 95 93 1 204 189 163 138 128 126 123 119 113 113 113 107 94 91 90 91 2 193 3 175 4 154 5 154 6 158 7 161 8 169 9 157 10 155 11 146 12 125 13 121 14 115 15 109 104 104 99 99 97 95 91 86 90 91 90 87 88 88 89 89 85 84 82 84 82 80 78 79 80 81 81 78 80 80 81 113 112 112 114 126 126 128 129 124 118 114 111 120 122 88 88 86 87 88 98 98 100 100 99 99 98 99 105 106 118 129 85 88 88 88 95 94 96 97 93 92 89 86 91 93 95 84 81 90 88 85 82 84 81 82 79 81 85 16 81 17 81 18 79 19 80 20 85 21 85 22 86 23 86 24 83 25 82 26 82 27 77 28 80 29 82 30 85 85 31 86 87 87 87 89 89 89 89 89 90 92 93 92 95 97 98 100 100 100 100 102 103 102 104 106 110 114 123 115 119 125 131
OUTPUT CHANNELS
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FN7432.0 February 24, 2006
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ISL59532
3dB Bandwidth, Broadcast Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 270 256 240 219 233 225 204 187 172 171 170 167 152 153 155 151 146 138 133 127 129 126 119 118 116 118 120 118 113 114 115 117 116 121 118 112 105 105 106 108 110 107 104 101 93 91 88 110 106 103 103 103 103 105 102 106 106 95 94 91 155 146 134 123 125 126 126 128 123 123 114 103 99 1 277 261 223 189 158 152 146 137 128 128 126 119 103 99 96 97 2 268 3 247 4 213 5 216 6 227 7 244 8 258 9 223 10 208 11 196 12 147 13 142 14 132 15 123 117 112 106 108 106 105 99 92 96 97 97 93 93 94 94 93 91 90 90 89 86 84 83 83 84 84 85 82 81 82 85 130 127 127 130 153 150 158 163 149 140 133 126 140 146 94 94 92 93 94 106 105 107 106 107 107 108 108 113 123 138 161 89 92 92 93 102 102 102 102 99 99 93 93 98 99 102 88 89 96 94 93 85 89 88 86 83 86 88 16 85 17 85 18 85 19 86 20 91 21 91 22 92 23 93 24 90 25 88 26 86 27 85 28 89 29 90 30 92 93 31 94 93 92 92 95 95 95 94 94 96 98 101 99 103 105 104 109 109 109 109 113 114 112 114 117 125 135 142 133 143 155 164
OUTPUT CHANNELS
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FN7432.0 February 24, 2006
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ISL59532
ISL59532 Block Diagram
VS+ VOVERn OVERn
32 OVERLAY INPUT 32 LOGIC CONTROL
REF
+
Power-on
32 INPUTS
Clamp Enable
SWITCH MATRIX
32 OUTPUTS
+
Av +1,+2
Output Enable
Power-on
SDI CLK ENA
SPI INTERFACE, REGISTER
SDO
General Description
The ISL59532 is a 32 x 32 integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) insertion. This device operates from a single +5V supply. Any output can be switched to any of the 32 input video signal sources and OSD information through an internal, dedicated fast 2:1 mux located before the output buffer. Also, any one input can be broadcast to all 32 outputs. The ISL59532 offers a -3dB signal bandwidth of 320MHz. The differential gain and differential phase of 0.025% and 0.05 respectively, along with 0.1dB flatness out to 50MHz. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPITM-compatible, three-wire serial interface. The ISL59532 interface is set up to facilitate both fast updates and initialization. On power-up, all facilities are initialized in the disabled state to avoid output conflicts within the user system.
Digital Interface
The ISL59532 uses a simple 3-wire SPI compliant digital interface to program the outputs. The ISL59532 can support the clock rate up to 5MHz.
Serial Interface
The ISL59532 is programmed through a three-wire serial interface. The start and stop conditions are defined by the ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The LSB (bit 0) is loaded first and the MSB (bit 15) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals.
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FN7432.0 February 24, 2006
ISL59532 Serial Timing Diagram
ENA tE
T
tr
tf
tHE
tSE
SCLK tSD tHD tw
SDI
B0 LSB
B1
B2
B12-B2
B14
B15 t MSB
LOAD MSB FIRST, LSB LAST
TABLE 1. SERIAL TIMING PARAMETERS PARAMETER T tHE tSE tHD tSD tW RECOMMENDED OPERATING RANGE 200ns 20ns 20ns 20ns 20ns 0.50 * T Clock Period ENA Hold Time ENA Setup Time Data Hold Time Data Setup Time Clock Pulse Width DESCRIPTION
Programming Model
The device has power-on reset that disables outputs, disables test mode, and turns off analog currents. To start up the device the control word is sent:
TABLE 2. CONTROL WORD FORMAT B15 1 B14 1 B13 1 B12 B11 B10 B9 Clamp B8 0 B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 Power on B0 Common output enable
It is important to always program control bits 2-8 as zeros to avoid activating test modes designed for device manufacturing.The clamp bit activates the input clamp and bleed current sink and works only in the single-ended version. To enable individual outputs, the output enable control word is sent. There are 32 enables to set; this is done with serial words controlling eight at a time. The output enable control word format is:
TABLE 3. OUTPUT ENABLE FORMAT B15 0 B14 0 B13 1 B12 B11 B10 B9 N1 B8 N0 B7 On+7 B6 On+6 B5 On+5 B4 On+4 B3 On+3 B2 On+2 B1 On+1 B0 On
The Ox bits represent output enables of eight individual registers. The N1N0 bits represent a two bit binary number which is used in setting n = 2N1N0. For instance, to access the control bit of the 11th output enable, we send the word:
TABLE 4. OUTPUT ENABLE WORD OF 2ND GROUP OF OUTPUTS B15 0 B14 0 B13 1 B12 B11 B10 B9 0 B8 1 B7 O15 B6 O14 B5 O13 B4 O12 B3 O11 B2 O10 B1 O9 B0 O8
Individual output enables are ended with the control register's common output enable bit and the power on bit. 20
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Gain Setting The gain of each output may be set to 1 or 2 using the gain set word. It is in the same format as the output enable control word:
TABLE 5. GAIN SET FORMAT B15 0 B14 1 B13 0 B12 B11 B10 B9 N1 B8 N0 B7 Gn+7 B6 Gn+6 B5 Gn+5 B4 Gn+4 B3 Gn+3 B2 Gn+2 B1 Gn+1 B0 Gn
Input to Output Selection Individual outputs receive their input selection choice using the input/output control word. Its format is:
TABLE 6. INPUT/OUTPUT WORD B15 0 B14 0 B13 0 B12 I4 B11 I3 B10 I2 B9 I1 B8 I0 B7 B6 B5 B4 O4 B3 O3 B2 O2 B1 O1 B0 O0
For a given binarily selected output, as specified by the O's, an input channel is assigned by the binarily selected I's. Thirty-two transmissions of the input/output control words will be required to set up all outputs. Broadcast Mode The broadcast mode routs one input to all 32 outputs. It has a memory bit that remembers its state. The configuration of input/output assignments that existed before setting broadcast mode is kept in memory and when broadcast mode is disabled the previous configuration is restored. The broadcast control word format is:
TABLE 7. BROADCAST WORD B15 0 B14 1 B13 1 B12 I4 B11 I3 B10 I2 B9 I1 B8 I0 B7 B6 B5 B4 B3 B2 B1 B0 EB
EB sets or resets the broadcast mode memory bit. The I's binarily select the input channel to be broadcast to all outputs.
NOTE: Going from broadcast mode to normal crosspoint mode can alter the input/output configuration. All input/output selections currently must be re-sent after a broadcast-to-non-broadcast transition.
Bandwidth Considerations
Wide frequency response (high bandwidth) in a video system means better video resolution. Four sets of frequency response curves are shown in Figure 47. Depending on the switch configurations, one can get between 250MHz to 350MHz bandwidth. A short discussion of the trade-offs follows--including matrix configuration, output buffer gain selection, channel selection, and loading.
2
Mux, Av = 2
mode. In addition, output buffer gain of +2 has higher bandwidth than gain of +1 due to internal device compensation. Therefore, the highest bandwidth set-up is multiplexer mode and output buffer gain of +2. The relative location of the input and output channel also has significant impact on the device bandwidth. Again this is due to the layout of the device. When the input and output channels are further away, there are additional parasitics as a result of the distance and lower bandwidth results. The bandwidth does not change significantly with resistive loading as shown in Figure 3 in the typical performance curves. However, it does change greatly with capacitance loading, Figure 4 in typical performance curves. This is most significant when laying out the PCB. If the PCB trace between the output of the crosspoint switch and the back termination resistor is not minimized, additional parasitic capacitance severely distorts the frequency response. To emphasize how critical the PCB layout is to performance, let's compare the two boards presented in Figures 48 and 49. Figure 48 shows a larger engineering evaluation board where the termination resistor is far away from the device because of the use of a socket. The board in Figure 48 is a
0 Normalized Gain [dB] -2 -4 -6 -8 -10 1 10 100 Frequency [MHz]
Broadcast, Av = 2 Broadcast, Av = 1
Mux, Av = 1
1000
FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES
In multiplexer mode, the input only drives one output channel, while in broadcast mode the same input drives all 32 outputs. The parasitic capacitance of all 32 channels loads down the input and reduces bandwidth in broadcast 21
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demoboard without the socket. The parasitic capacitance of the demoboard is about 2.7pF less.
0.0
Demo
-1.2
Eng Eval
-2.4 Gain [dB] -3.6 -4.8 -6.0
1
10 Frequency [MHz]
100
FIGURE 50. FREQUENCY RESPONSE - ENG EVAL BOARD vs DEMO
Linear Operating Region
FIGURE 48. ENGINEERING EVALUATION BOARD
In addition to bandwidth, one must also be very careful with operating the device at its linear operating region. Figure 51 shows differential gain curve. The ISL59532 is a single supply 5V device with its linear region is between 0.1 and 2V. The signal range is fine for most video signals whose nominal signal amplitude is 1V. Both inputs should be maintained at 0.3V or above for best operation. A DC restore circuit is required to put the video signal within the linear operating region of the crosspoint switch.
FIGURE 49. CUSTOMER DEMOBOARD FIGURE 51. DIFFERENTIAL GAIN RESPONSE
To prove that the parasitic capacitance is the largest contributor to the difference in bandwidth of the two boards, we added 2.7pF at the output of the demoboard. Figure 50 shows the similarity in frequency response of the engineering evaluation board alongside the demoboard piggybacked with 2.7pF.
The high quality differential gain performance is provided by a DC restore clamp circuit at the input of the device. A discussion of the benefits of the DC-restored system begins by understanding the block diagram of a DC-restore (Figure 52). It consists of 4 simple sections: an input RC network, an op amp configured as a buffer, a FET switch, and a current source. In the absence of an input signal, Rin drains the input node to ground. The discharge current drains the input capacitance of charge to restore the output of the block to ground in preparation for when the FET switch is turned on. This action eliminates any intensity abnormalities.
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VDD
Vref
+
Where: * TJMAX = Maximum junction temperature = 125C * TAMAX = Maximum ambient temperature = 85C * JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
n
Iclamp Charge Iclamp discharg
Vin
Rin
Cin
FIGURE 52. DC RESTORE BLOCK DIAGRAM
PD MAX = V S x I SMAX +
i=1
( VS - VOUTi ) x ----------------R Li
V OUTi
The pulldown current is necessary to enable the clamp action each sync time but causes the signal to droop during the rest of the video waveform. This droop rate is IB/Cin volts/second. We generally limit the droop voltage to <1 IRE over a period of video; so for 1 IRE = 7mV, IB = 10A maximum, and an NTSC waveform we will set Cin > 10A*60s/7mV = 0.086F. Figure 53 shows the result of Cin = 0.1F delivering acceptable droop and Cin = 0.001F producing excessive droop.
Where: * VS = Supply voltage = 5V * ISMAX = Maximum quiescent supply current = 700mA * VOUT = Maximum output voltage of the application = 2V * RLOAD = Load resistance tied to ground = 150 * N = 1 to 32 channels
n
PD MAX = V S x I SMAX +
i=1
( VS - VOUTi ) x ----------------- = R Li
V OUTi
4.8W
The reqired JA to dissipate 4.8W is:
T JMAX - T AMAX JA = -------------------------------------------- = 8.33 ( C W ) PDMAX
FIGURE 53. DC RESTORE VIDEO WAVEFORMS
Power Dissipation and Thermal Resistance
With a large number of switches, it is possible to exceed the 150C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the crosspoint switch in a safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
Table 8 shows JA thermal resistance results with a Wakefield heatsink and without heatsink and various airflow. At the thermal resistance equation shows, the required thermal resistance depends on the maximum ambient temperature.
TABLE 8. JA Thermal Resistance [C/W] Airflow [LFM] No Heatsink Wakefield 658-25AB 0 18 16.0 250 14.3 7.0 500 13.0 6.0 750 12.6 4.7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 23
FN7432.0 February 24, 2006
ISL59532
356 Ld BGA Package
24
V356.27x27A
FN7432.0 February 24, 2006

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